The present invention relates to an MOS transistor logic circuit.
Recently, MOS integrated circuit techniques have been greatly advanced, and many types of logic circuits for use in an electronic calculator are made of complementary MOS transistors. However, it is not preferable that all circuit components are made of complementary MOS transistors. This is because the same number of P-channel MOS transistors and N-channel MOS transistors are required in the above-mentioned types of logic circuits and, hence, the LSI chip size becomes larger than necessary.
To reduce the chip size, clocked complementary MOS transistor circuits are proposed. However, the conventional clocked complementary MOS transistor circuits are not satisfactory, because the clock pulses are not effectively used in the conventional clocked complementary MOS transistor circuits and the logic circuit is made of the same number of P-channel MOS transistors and N-channel MOS transistors.
Accordingly, an object of the present invention is to provide an MOS transistor logic circuit of a small chip size.
Another object of the present invention is to provide an MOS transistor logic circuit, wherein clock pulses are effectively utilized.
Still another object of the present invention is to provide an MOS transistor logic circuit including a plurality of stages of logic gates, which can be driven by three-phase clock pulses.
Yet another object of the present invention is to provide an MOS transistor logic circuit of low power dissipation.
Other objects and further scope of applicability of the present invention will become apparent from the detailed description given hereinafter. It should be understood, however, that the detailed description and specific examples, while indicating preferred embodiments of the invention, are given by way of illustration only, since various changes and modifications within the spirit and scope of the invention will become apparent to those skilled in the art from this detailed description.
To achieve the above objects, pursuant to an embodiment of the present invention, three-phase ratioless MOS transistor circuits and complementary MOS inverter circuits are incorporated in an integrated MOS transistor logic circuit. The three-phase ratioless MOS transistor circuit includes a logic circuit made of MOS transistors of one conductivity type, whereby the chip size is greatly reduced.